1. Field of the Invention
The present disclosure relates to a technology for reducing flicker in generating a gate pulse modulating signal at the time of overlapping driving of a GIP (Gate in panel) panel, and more particularly, to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter.
2. Discussion of the Related Art
A related art liquid crystal display device controls a light transmissivity of liquid crystals by using an electric field for displaying a picture. To do this, the liquid crystal display device is provided with a liquid crystal panel having a matrix of pixel regions and a driving circuit for driving the liquid crystal panel.
The liquid crystal panel has a plurality of gate lines and a plurality of data lines arranged perpendicular to each other. A pixel region is positioned at every region defined as the gate lines and the data lines cross each other perpendicularly. Pixel electrodes and a common electrode are formed on the liquid crystal panel for applying an electric field to the pixel regions.
Each of the pixel electrodes is connected to the data line through a thin film transistor TFT, which is a switching device. The thin film transistor has a gate electrode, a source electrode and a drain electrode. The thin film transistor is turned on in response to a scan pulse applied to the gate electrode via the gate line, and supplies a data signal on the data line to the pixel electrode.
The driving circuit has a gate driver for driving the gate lines, and a data driver for driving the data lines, a timing controller for supplying a control signal to control the gate driver and the data driver, and a power source unit for supplying various driving voltages for the liquid crystal display device.
The timing controller controls driving timings of the gate driver and the data driver, and supplies a pixel data signal to the data driver. The power supply unit receives a voltage and pulls up/down the voltage for generating driving voltages the liquid crystal display device requires, such as a common voltage VCOM, a gate high voltage signal VGH, a gate low voltage signal VGL, and so on. The gate driver supplies a scan pulse to the gate lines in succession for driving one line portion of liquid crystal cells on the liquid crystal panel in succession. The data driver supplies a pixel voltage to each of the data lines every time the scan pulse is supplied to one of the gate lines.
The liquid crystal display device accordingly individually controls the light transmissivity of the liquid crystal cells by the electric field applied between the pixel electrode and the common electrode according to the pixel voltage, thereby displaying the picture.
In this instance, as described, the gate driver is provided with a shift register for forwarding the scan pulses in succession. There is a recent trend in widely using a GIP (Gate In Panel) technology, in which the gate driver is formed in the panel.
The liquid crystal display device has a problem in that a picture quality thereof becomes poor due to flickers caused both by differences of variation of positive and negative pixel voltages charged at the pixels with variation of parasitic capacitance in the thin film transistor and the gate voltage at the time the thin film transistor is turned off, and the increased load (resistance and capacitance) on the gate line come from an increased size of the liquid crystal display device which increases delay of the scan pulse that results in shortage of time for the thin film transistor to charge a data.
Consequently, in order to solve the problem, GPM (Gate Pulse Modulation) is used, which is operated in synchronization with at least two clock signals (2-phase non-overlapping clock) having portions overlapped with each other.
FIG. 1 illustrates a block diagram of a related art gate pulse modulation signal generating circuit.
Referring to FIG. 1, the related art gate pulse modulation signal generating circuit is provided with gate pulse modulation units 41A and 41B for receiving flicker preventive signals FLK1 and FLK2 and generating gate-on voltage modulation signals VGHM1 and VGHM2 respectively, level shifters 42A and 42B for receiving clock signals (ICLK1 and ICLK3), and (ICLK2 and ICLK4) from the timing controller and generating 2H interval, VGL˜VGH level modulated odd and even line clock signals (CLK1 and CLK3), and (CLK2 and CLK4) respectively, and a GIP 43 for receiving the clock signals (CLK1 and CLK3), and (CLK2 and CLK4) from the level shifters 42A and 42B and generating and forwarding modulated gate output signals (GATE OUTPUT N−1), (GATE OUTPUT N), (GATE OUTPUT N+1) to the gate lines of the liquid crystal panel. The GIP 43 is a built-in type gate output circuit. That is, the GIP 43 is formed in the liquid crystal panel while rest of element is formed on an outside of the liquid crystal panel.
The operation of the related art gate pulse modulation signal generating circuit will be described.
FIGS. 2A˜2G illustrate waveforms for showing generating steps of a gate pulse modulation signal in a related art overlapping drive, FIGS. 3A˜3D illustrate waveforms of related art clock signals respectively, and FIGS. 3E˜3H illustrate waveforms of related art level shifted and modulated clock signals respectively.
The gate pulse modulation unit 41A receives a flicker preventive signal FLK1 as shown in FIG. 2A and the gate high voltage VGH from the timing controller and generates a gate-on voltage modulation signal VGHM1 as shown in FIG. 2B. The gate high voltage VGH is a high logic voltage of the scan pulse set higher than a threshold voltage of the TFT.
Alikely, the gate pulse modulation unit 41B receives a flicker preventive signal FLK2 as shown in FIG. 2C and the gate high voltage VGH from the timing controller and generates a gate-on voltage modulation signal VGHM2 as shown in FIG. 2D.
The level shifter 42A receives the gate-on voltage modulation signal VGHM1 from the gate pulse modulation unit 41A, the clock signals (ICLK1 and (CLK3) as shown in FIGS. 3A and 3C from the timing controller (not shown) and generates a level shifted and modulated odd line clock signal (CLK1 and CLK3) as shown in FIGS. 3E and 3G. The gate low voltage VGL is a low logic voltage of the scan pulse set as a turn-off voltage of the TFT.
The level shifter 42B receives the gate-on voltage modulation signal VGHM2 from the gate pulse modulation unit 41B, the clock signals (ICLK2 and (CLK4) as shown in FIGS. 3B and 3D from the timing controller and generates a level shifted and modulated even line clock signal (CLK2 and CLK4) as shown in FIGS. 3F and 3H.
The GIP 43 which is a gate driver IC built-in the panel receives the four phase clock signals CLK1, CLK2, CLK3 and CLK4 from the level shifters 42A and 42B and the VGH and VGL voltages and generates and forwards modulated gate output signals (GATE OUTPUT N−1), (GATE OUTPUT N) and (GATE OUTPUT N+1) as shown in FIGS. 2E, 2F and 2G to the gate lines of the liquid crystal panel.
If the overlapping driving is used as the gate driving, since the gate output signal has 2H intervals, the gate modulation signal can not be forwarded to a (2n)th (even numbered) line and a (2n+1)th (odd numbered) line by using one clock signal FLK. Therefore, in the related art, two gate-on voltage modulation signals VGHM1 and VGHM2 are generated by using two clock signals FLK of different phases, and the gate-on voltage modulation signal VGHM1 is applied to the odd numbered line and the gate-on voltage modulation signal VGHM2 is applied to the even numbered line, to enable to output the gate modulation signal even in the overlapping driving.
As described, in order to embody the gate pulse modulation of the overlapping driving in the GIP liquid crystal display device, a plurality of clock signals FLK are required. That is, two flicker preventive signals FLK are required (See FIG. 1) for four phased driving, and three flicker preventive signals FLK are required for six phased driving.
That is, FIG. 4 illustrates a timing diagram for explaining a problem of the gate pulse modulation in a case only one flicker preventive signal FLK is used in the related art.
Referring to FIG. 4, in the case only one flicker preventive signal FLK is used, a dip takes place at the modulated gate output signals (GATE OUTPUT N) and (GATE OUTPUT N+1), making reliability of the driving of the liquid crystal display device poor.
Three flicker preventive signals FLK are required for six phased driving.
FIG. 5 illustrates a block diagram of a related art level shifter for the six phased driving.
FIG. 5 illustrates a case the gate pulse modulation unit is merged to the level shifter.
From the timing controller (not shown), three flicker preventive signals FLK1, FLK2 and FLK3 are forwarded to the gate pulse modulation unit GPM, and the gate high signals VGH1 and VGH2 and six clock signals GCLK1, GCLK2, GCLK3, GCLK4, GCLK5 and GCLK6 are forwarded to the level shifter L/S.
Since the timing controller is required to apply the three flicker preventive signals FLK1, FLK2 and FLK3 and the six clock signals GCLK1, GCLK2, GCLK3, GCLK4, GCLK5 and GCLK6 to the level shifter L/S, numbers of input/output pins of the timing controller and the level shifter are increased.